The invention is related to a special character sequence detection circuit arrangement of a time-multiplex digital telecommunications system for evaluating data characters sent out by one of a multiplicity of data terminals adapted to be connected to a central exchange control of the telecommunications system and scanned cyclically. The established set of data characters includes special characters which, when sent out repetitively a predetermined number of times, are determined by the central exchange control for triggering a corresponding control process.
Fully electronic computer-controlled switching systems for handling digital communication services are wellknown in the art. Such switching systems are flexibly designed for use in different applications such as worldwide telex and gentex networks and may be used either as public or as private data networks or as integrated networks. A system of this type is described in a copending patent application, Ser. No. 199,202 filed Oct. 29, 1980, now allowed. The central exchange control of this telecommunication system is composed of modular hardware and software components. The hardware essentially comprises a central processing system which performs the main control functions, especially for establishing through-connections between pairs of data terminals and for terminating such connections. A communications hardware module connects subscriber lines or trunk lines to the central exchange control and controls time-multiplex operations during the transfer of messages between through-connected subscriber lines. It comprises a communications controller operating under program control of the central processor, terminator group controllers forming a logic interface between the communications controller and line terminators which provide the peripheral communication links to subscriber lines and trunk lines. The line terminators receive data at various speeds and in different codes and present formated data to the communications controller across an associated terminator group controller and transmit correspondingly processed output data to the associated subscribers or data terminals. The central processor system and other parts of the communications hardware, as well are duplicated in the central exchange control for reasons of reliability.
These hardware modules are supported by software modules such as an operating system and a maintenance system. A control system is the central and control-oriented part of the operating system and accomplishes central control functions. A switching system provides all functions for switching-oriented operations and controls all phases of a connection from an initial call request to final clear-down and disconnect.
Such computer-controlled switching systems are designed to be easily adjustable to different kinds of applications for use as a terminal exchange, a tandem (transit) exchange, an international gateway exchange, or a PABX for direct-connection mode. The desired flexibility requires a high level of switching capabilities for handling different kinds of high speed data traffic that is achieved by a variety of optional features.
One possibility to implement such optional features and to initiate corresponding processing routines in the central exchange control is the use of special data characters sent out by an initiating data terminal repetitively and a predetermined number of times. When received by the central exchange control the sequence of special characters is recognized and evaluated for triggering a corresponding process control. The communications controller, therefore, includes means for recognizing special characters and determining a special character sequence when the same special character occurs directly consecutively in a predetermined sequence.
A corresponding circuit arrangement is described in the U.S. Pat. No. 4,192,966. The known circuit arrangement can be used to trigger control processes only in the event that data characters consisting of an established sequence of "elements" have occurred in a likewise established frequency directly consecutively in the sequence of characters. The known circuit arrangement is provided with a memory which emits control signals to an evaluation circuit only when a received data character is composed of special sequence character elements. A counter is connected to the output of the evaluation circuit which is designed in such a manner that only by emission of the specific control signals, it is able to trigger counting processes in a counter. The counter executes a counting process only in the event that a control signal with which it has been supplied by the evaluation circuit is identical to the previously occurred control signal. If a control signal is generated which differs from the previous control signal supplied to the counter, the counter is reset to an established count.
The detection device of the known circuit arrangement is implemented in the form of a programmable read-only memory which offers the possibility to change addresses and codes for special characters, but the design evidently is aimed at only a limited use of a special character feature. The read-only memory is of limited capacity and the basic structure of the circuit arrangement requires that the special characters of a sequence are received at the evaluating memory directly consecutively. Apparently no provisions are made to correspond to the characteristic of a digital telecommunication network enabling transfer of a multiplicity of data messages simultaneously on a character-by-character basis in a time multiplex mode.
It may be envisioned that the known circuit arrangement can be integrated into the central exchange control of such a digital telecommunications system. A first possibility is to buffer all data characters transmitted from the different line terminators for several scan cycles, thereby establishing a short term history of the entire data traffic. If the characters are buffered in stacks each associated with a respective line terminator the sequences can be evaluated directly consecutively by a high speed detection circuit arrangement. Another possibility would be to provide a multiple circuit arrangement for detecting a special character sequence such that individual circuit arrangements are associated with a specific one of the data sources. If these individual circuit arrangements are triggered in synchronism with the scan cycle, they will be activated only when the associated line terminator is sending a data character. The first solution requires quite an outlay of memory space just for this special feature and would slow down the through-put rate of data. The second possibility would not be very efficient, since it necessitates an unjustified amount of hardware. Both possibilities are in contrast to the basic design of the central exchange control which provides a constantly updated version of current connection conditions and avoids buffering of data characters to be transferred whenever possible to speed up data through-put.
In addition, because of the desired flexibility of the central exchange control for different applications, the two degrees of freedom inherent to a special sequence feature should be really used. The circuit design should be such that the special characters can be sign should be such that the special characters can be reassigned easily without a hardware redesign of the circuit and the length of a sequence consisting of a plurality of data characters should be more freely selectable.